An integrated circuit is a miniaturized electric circuit that comprises a large number of elementary components such as conductors, diodes, transistors, transmission lines, capacitors, and inductors. The elementary components and their mutual distances within an integrated circuit have become smaller and smaller as a consequence of progress in manufacturing techniques. The various processing techniques and also the resulting circuits may be classified by referring to so-called technology nodes. A technology node comprises methods capable of producing integrated circuits with a certain smallest possible distance between neighboring components in the circuit. For instance, the 130 nanometer technology node refers to production methods of devices with a gate length of 130 nm.
For technology nodes of 130 nanometers and less, i.e., for 130 nanometer technology nodes and more recent technology nodes, it is an established technique to place tile shapes during a layout finishing flow in order to ensure planarization. Tile shapes are also known as fill shapes. The circuit layout including the tile shapes may then be analyzed in order to verify whether it satisfies a density rule, or a set of density rules. Defined regions of a layer or surface within the integrated circuit may be assigned density values. A density rule is a set of one or more constraints on density values associated with such regions. A density value of a certain region may be defined as the area covered by a certain type of components located within that region relative to the total area of the region. For example, a variation of density values across the entire layer or surface may be required not to exceed a maximum allowed density variation. Components of different types, e.g., metal and silicon, may be assigned separate density values.
Regions in which transistors are to be implanted may be referred to as active regions or active areas. Active regions may also be subject to density rules. To this end, tile shapes may be provided in addition to the functional components. The tile shapes may, in principle, consist of any material suitable for satisfying the density rules in question. A tile shape in a certain layer of the integrated circuit may be formed of the basic material of that layer, e.g., metal or polysilicon. If, for example, an area covered by a combination of fill shapes and metal shapes does not meet specific density criteria, a circuit designer may have to place additional fill shapes manually or with the help of automated tools.
For technology nodes of 90 nanometers and more, the tile shapes usually have a negligible effect on the electrical performance of the integrated circuit. However, for technology nodes of 65 nanometers and less, the tile shapes may affect the electrical performance of the integrated circuit to an extent that can no longer be ignored. For example, placing tiles near analog devices such as transistors or resistors may affect the electrical behavior of the circuit by creating an additional coupling capacitance.
FIG. 1 schematically illustrates an example of a first method of designing an integrated circuit.
First, a schematic layout of the circuit may be generated (block 1.1). The schematic layout may be generated manually, automatically, or by a combination of manual and automatic operations, starting from, e.g., a list of functional components and connecting lines. A number of characteristics of the circuit, e.g., geometrical parameters such as dimensions and positions of the various components, or dielectrical properties, may still be undefined in the schematic layout.
A physical design may then be generated on the basis of the schematic layout (block 1.2) by determining additional characteristics of the circuit. The additional characteristics may, for example, include the dimensions and positions of the various components of the circuit. The dimensions and positions may, for example, be determined on the basis of a set of design rules and with the aim of making the circuit as small as possible.
A post-layout simulation may then be performed on the basis of the physical design, resulting in electrical simulation data (block 1.3). Depending on the electrical simulation results, the circuit designer or an automated design tool may then alter design parameters or instance parameters of the schematic layout (block 1.1). In this approach, simulating operation of the circuit (block 1.3) may enable the circuit designer to study the behavior of the circuit as defined by the physical design of block 1.2. The electrical simulation, however, usually does not take into account the possible effects of tile shapes that may be added to the circuit, as this would generally have a major impact on the simulation time. Instead, tiles shapes are usually added to the physical design (block 1.2) during a chip finishing flow. The placement of tile shapes may therefore be suboptimal in view of its electrical interaction with the rest of the circuit. Furthermore, the electrical impact of the tile shapes may be difficult to assess.
FIG. 2 schematically shows an example of a chip 10 providing an integrated circuit. The chip 10 may comprise a plurality of functional components. Two functional components 12 are shown in the Figure. Each functional component may be an elementary component such as a transistor or a capacitor or a more complex component composed of elementary components. Although only two functional components 12 are shown in the Figure, a chip may, in practice, comprises tens or thousands of functional components.
FIG. 3 shows the example of a chip 10 after an operation of adding tile shapes 14 to the chip. Each tile shape represents a physical component formed of, e.g., a layer material, e.g., an active, polysilicon or metal layer.
At least one of the functional components 12 may, for example, represent an analog block, e.g., for treating an analog signal received at circuit inputs. Depending on various design considerations, the analog blocks may or may not be tiled, i.e., they may or may not be covered by tile shapes 14.
The chip 10 may, for example, be represented numerically using a dedicated chip design tool such as the “cadence” environment. The tool may allow the program designer to enter geometrical or electrical parameters or both in a phase of generating a schematic layout similar to the schematic layout shown in block 1.1 of FIG. 1. Special code callbacks may allow to calculate suitable values of geometrical parameters if values of electrical parameters have been entered. The geometrical parameters may be used to automatically produce layouts matching these parameters. A spice model may enable simulating a behavior of the device with geometrical or electrical inputs.
As mentioned above, tile shapes are usually not taken into account in the electrical simulation of the circuit (post layout simulation), as this would significantly increase the simulation time. Furthermore, tile shapes are usually not taken into account in any pre-layout simulation.